TOPSECCRET: Implementation
The Structure
Two terminals, constructed nearly identically, are connected
via a databus. Encryption and decryption occurs on both terminals, and
data is sent in both directions over the bus. The input is taken from two
32-key keypads (a total of 64 keys per terminal) and sent in the form of
5 data bits. A sixth bit is used for the parity check, and the remaining
two bits supported by the 8-bit data bus are unused. The input and
the parity bit are encrypted with password bits read from EEPROM, and the
octal buffer outputs are enabled in order to transmit the data over the
bus. The board on the receiving end decrypts the data with password bits
read from the same location on its identical copy of the EEPROM, and then
clocks in the decrypted data from the bus with a D flip-flop. The data
from the D flip-flop is sent to the displays (3 bits to one display, 2
bits to the other), and the parity bit is checked.
The Phases
In order for the terminal A and
terminal B to transmit and receive
data encrypted with the same password data, at the same time, and to ensure
that password data was not reused, a cycle of phases, or states, was developed.
The terminals cycle through these phases in order, using a synchronized
master clock signal. The master clock signal is split into several specialized
timing signals which control the various components of the circuit. Specifically,
the counter which addresses the EEPROM, the octal buffer which outputs
to the data bus, and the D flip-flop which reads from the data bus. A graph
of the signal timings used to control the chips is below:
During the Processing phases, the counter addressing the EEPROM
is clocked with a rising edge (and thus incremented), and the new password
data is read off the EEPROM. During the first half of the Transmitting/Receiving
phase, the transmitting board activates the octal buffer's outputs (by
providing a low signal to the OE' of the buffer), taking control of the
bus lines. After the lines have had time to settle at the correct values,
at the start of the second half of the Transmitting/Receiving phase, the
receiving board clocks its D flip-flop with a rising edge, receiving the
data.
The Clocks
The clock signals in the above diagram must be generated from a master
clock signal, which both terminals must draw from the same source to ensure
that they are synchronized. A 555 timer chip
was used to generate the master clock signal, which was then sent to both
terminals. Both terminals use a pair of JK flip-flops (initialized to the
low state) in order to split up the incoming clock signal (label them JK1
and JK2). Both of the JK flip-flops are permanently
set in "toggling" mode. JK1 receives its clock from the master clock signal,
and JK2 receives its clock from JK1's Q output.
On terminal A the clocks are generated
as follows:
Counter Clock: JK1Q'
Buffer Enable: JK1Q'
OR JK2Q
D flip-flop Clock: 555
AND JK1Q AND JK2Q
On terminal B, the clocks are generated
similarly, with JK2Q' substituted for JK2Q:
Counter Clock: JK1Q'
Buffer Enable: JK1Q'
OR JK2Q
D flip-flop Clock: 555
AND JK1Q AND JK2Q
Thus, the only difference between the two terminals is that all connections
to JK2 are inverted.
Problems Encountered
Many problems were encountered during the actual construction of
this circuit. Aside from the occasional misplaced wire, severe noise problems
resultant from depleted battery power packs repeatedly caused bugs. Attempting
to use an AC to DC power pack converter only made the problems worse. The
only solution was to purchase fresh batteries whenever the current set
became about halfway depleted. One problem that was difficult to locate
with the keyboards. Pressing keys resulted in the proper values only about
half the time, and the problem was tracked to a missing key debounce capacitor.
After accelerating our clock, the board appeared to function properly for
quite some time. It later ceased to function, and the problem was tracked
to the accelerated clock speeds. Finally, one of the most difficult problems
to diagnose involved the layout of the wires running between the terminals.
Electromagnetic interference from the data bus lines was affecting the
clock signal wire (which had been running parallel to the bus lines in
a bundled group of wires). The interference caused the JK flip-flops on
one board to clock out of synch with the other board. This in turn affected
the counters connected to the EPROMs, causing a complete breakdown of communications.
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TOPSECCRET -- It sounded simple enough.....