EE150: Digital Logic Project: Bomb Detonator
         
    The purpose of the project was to create a working "bomb detonator" which consisted of a modulo-6 and a modulo-10 counter combined to create a 60 second countdown timer. This timer, which starts at 59 seconds, counts down to 00 and freezes the timer. The mod-6 timer used D flip-flops, while the mod-10 timer used J-K flip-flops.This webpage displays the work of Simon Goldburd and  Himel Barua in performing the project

    The first step in the process was drawing up state tables for both the modulo-6 and modulo-10 counters.

    To see the state tables for each counter go here.

    Here are the state diagrams:
                                                                                     Mod 6

                                                        Mod 10

     
     

    Once the state tables were complete, the process of drawing up Karnaugh maps for each counter was accomplished.

    PLEASE NOTE : The Karnaugh maps for Ja and Ka are not shown; they all reduce to one

    Here are the Karnaugh maps for all J,K, and D values:
     

                        Mod 6
                        Mod 10

     
     


     

    The next step was creating the logic, board, and circuit diagrams.

    Logic Diagram

        In connecting the circuit, a clock pulse for both the modulo-6 and modulo-10 counters were needed. However, while the mod-10 counter had to have a clock pulse of one second and therefore derived its pulse from a 555 timer chip, the mod-6 counter had to have a clock pulse only when the mod-10 counter had a value of 9 (The tens place changes when the one's place changes from 0 to 9). To solve this problem a comparator chip was used. However, since there were only two comparators available in the creation of the project and the clock had to be stopped at 00 seconds (requiring both comparators to be set at 0 for comparison), a problem arose in which the mod-6 counter went off at 0 instead of 9. Knowing that the D flip-flops (which were used in the creation of the mod-6 counter) changed on the rising edge of the clock pulse, a NOT gate was used to solve the problem. Inverting the clock pulse to the mod-6 counter using the NOT gate created a value of HIGH for the clock pulse to mod-6 counter when values of the mod-10 were between 1 and 9. On a 0 the clock pulse gave a low. Then upon changing back to 9, a rising edge of a clock pulse was giving, clocking the mod-6 counter at 9.

    As mentioned above, one of the requirements for the project was to stop the countdown at 00 (as opposed to letting the circuit reset back to 59...). To do this required two steps:
                1)  Learning when the 00 state was active
                2)  Freezing the clock

    To solve these conditions, two comparator chips were used: one to detect 0 with the mod-10 counter(which also provided the clock pulse for the mod-6 counter as described above) and another one to detect 0 with the mod-6 counter. The outputs of both comparator chips were wired to an NAND gate, in turn whose output was wired to the "ENABLE" pin of the 555 timer chip. When the "ENABLE" pin on the 555 timer chip is HIGH, the timer runs normally. However, when it is set to low the timer is disables. When both of the comparators produced at 1 as an output(at the 00 state), the NAND gate, which normally produces an output of HIGH, creates a LOW output, thereby freezing the timer. Since the timer provides the clock pulse for the mod-10 counter, which in turn dictates when there will be a clock pulse for the mod-6 counter, the circuit freezes at 00.

    Below are links to the logic diagrams of the mod-6 and mod-10 counters, as well as for the comparator chips:

                Mod-6
                Mod-10

    •     Comparator
     

    Board Diagram
    Mod10

    Mod 6


     
     

    Circuit Diagram
      MOD 10
    MOD 6
    WHOLE BOARD